1. Field of the Invention
The invention relates to a manufacturing method for a metal gate, and more particularly, to a manufacturing method for a metal gate integrated with the gate last process.
2. Description of the Prior Art
Polysilicon is conventionally used as the gate electrode in a semiconductor device, such as the metal-oxide-semiconductor (MOS) transistor. However, with a trend toward scaling down the size of the semiconductor device, the conventional polysilicon gate has faced problems such as inferior performance due to boron penetration and unavoidable depletion effect which increases equivalent thickness of the gate dielectric layer, reduces gate capacitance, and worsens a driving force of the devices. Therefore, work function metals are used to replace the conventional polysilicon gate to be the control electrode that competent to the high dielectric constant (hereinafter abbreviated as high-k) gate dielectric layer.
Conventional manufacturing methods for metal gates are categorized into the gate first process and the gate last process. In a conventional manufacturing method for a metal gate applied with the gate first process, the anneal process for forming the source/drain ultra-shallow junction, and the silicide process are performed after forming the metal gate. The thermal budgets always make the gate first process face challenges for material choices. Consequently, the gate last process is developed to provide more material choices for the high-k gate dielectric layer and the metal gate, and thus replaces the gate first process.
Please refer to FIGS. 1-2, which are schematic drawings illustrating a conventional manufacturing method for a metal gate. As shown in FIG. 1, a substrate 100 is first provided with a dummy gate or a replacement gate 120 formed thereon. The dummy gate 120 includes a high-k gate dielectric layer 102, a titanium nitride (TiN) layer (not shown) serving as a bottom barrier layer, and a polysilicon layer 104 defined by a patterned hard mask (not shown). The dummy gate 120 has a height h1 that is almost equal to a thickness of the polysilicon layer 104. More important, the height h1 of the dummy gate 120 is to be a height of a following formed metal gate. After forming elements for the n-type transistor or p-type transistor such as lightly-doped drains (LDDs) 106, a spacer 108, and a source/drain 110, and other elements such as silicides 112, a contact etch stop layer (CESL) 114, and an inter-layer dielectric (ILD) layer 116, the conventional gate last process is to remove the polysilicon layer 104 of the dummy gate 120.
Please still refer to FIG. 1. During removing the polysilicon layer 104, a planarization process, such as a chemical mechanical polishing (CMP) process is performed to remove a portion of the ILD layer 116 and the CESL 114, thus the patterned hard mask is exposed. Then, another CMP process is performed to remove a portion of the ILD layer 116, the CESL 114, and the patterned hard mask to expose the polysilicon layer 104. Because an etching rate of the polysilicon layer 104 is significantly different from etching rates of the ILD layer 116, the CESL 114 and the patterned hard mask that all include insulating material, the CMP process is supposed to stop at the polysilicon layer 104 and thus exposes the polysilicon layer 104. However, it is found that the CMP process always consumes the polysilicon layer 104 at edges of the polysilicon layer 104, particularly at where the polysilicon layer 104 adjoining the patterned hard mask, even at wherein the polysilicon layer 104 adjoining the spacer 108. Consequently, the edges of the polysilicon layer 104, even the spacer 108, is consumed and removed by the CMP process and thus a height deviation is resulted between the center of the polysilicon layer 104 and the edges of the polysilicon layer 104. As shown in FIG. 1, the center of the dummy gate 120 has the original height h1 while edges of the dummy gate 120 have a reduced height h2 due to the CMP consumption. More important, the original height h1 is larger than the reduced height h2.
Please refer to FIG. 2. Next, the polysilicon layer 104 of the dummy gate 120 is removed to form a gate trench 130. It is noteworthy that the original height h1 of the removed dummy gate 120 is depicted by the dashed line in FIG. 2 for emphasizing the height deviation. A metal gate (not shown) is subsequently formed in the gate trench 130, and the metal gate inherently obtains the reduced height h2. Accordingly, the reduced height h2 of the metal gate formed by filling the gate trench 130 with work function metal material and filling metal material is not the same with the original and predetermined height h1 of the dummy gate 120, which means the metal gate unavoidably and undesirably suffers height loss. In other word, the reduced height h2 of the metal gate is significantly lower than an expected value, and thus the reliability and the electrical performance of the metal gate are adversely impacted.
Accordingly, though the gate last process is able to avoid processes of high thermal budget and to provide more material choices for the high-K gate dielectric layer and the metal gate, the gate last process still faces integration requirements for the complicated processes.